The present invention relates in general to data processing systems, and in particular, to a leading zeros anticipator used in floating-point pipelines.
Typically, floating point pipelines provide some means for renormalizing floating point data after performing some arithmetic operation, such as an add, multiply, divide, or subtract. Recall that a normalized number is one in which there is exactly one leading xe2x80x981xe2x80x99 prior to the binary point in the mantissa. Since the result of the leading xe2x80x981xe2x80x99 after an arithmetic operation may vary prior to normalization, the position of the leading xe2x80x981xe2x80x99 must be calculated prior to normalization.
For any arithmetic operation which performs an effective add of the operands (in which xe2x80x9ceffective addxe2x80x9d is defined as the addition of two positive or two negative operands, or the subtraction of a negative operand from a positive operand), the position of the leading xe2x80x9c1xe2x80x9d in the sum is easily calculated within a one binary-digit uncertainty by comparing the magnitudes of the operands"" exponents and choosing the position of the leading xe2x80x9c1xe2x80x9d in the operand with the largest exponent.
For an effective subtract operation, the operands may result in massive cancellation, and a large number of leading zeros may be generated in the resulting sum. The position of the leading xe2x80x9c1xe2x80x9d can be detected by either a xe2x80x9cLeading Zeros Detectorxe2x80x9d (LZD) circuit, or anticipated by a xe2x80x9cLeading Zeros Anticipatorxe2x80x9d (LZA) circuit.
A xe2x80x9cLeading Zeros Detectorxe2x80x9d is typically implemented as an N-way xe2x80x9cORxe2x80x9d gate, one for each bit position in the sum. Each bit is an effective xe2x80x9cORxe2x80x9d of all the preceding bits. In this way, a vector is generated which indicates the position of the first leading xe2x80x9c1xe2x80x9d in the sum. A disadvantage of the LZD is that it introduces additional delay because the sum must be completed before the leading zero may be detected.
A xe2x80x9cLeading Zeros Anticipatorxe2x80x9d avoids some of this additional delay by computing or anticipating the position of the first leading xe2x80x9c1xe2x80x9d in parallel with the final add which generates the sum. In this way, much of the delay of the LZD can be xe2x80x9chiddenxe2x80x9d, at the cost of some slight additional hardware.
A disadvantage of the LZA is that not all of the extra delay can be hidden. Typically, the output of the LZA is encoded to provide two functions (typically in the next pipeline stage). The first function, is a xe2x80x9cCount Leading Zerosxe2x80x9d (CLZ) value which is simply a binary representation of the position of the first leading xe2x80x9c1xe2x80x9d in the sum. The second function provided by the LZA is that of the normalizer mux (multiplexor) selects, also used in the next pipeline stage. This encoding for either function can be very time-consuming and delays the normalization process.
Many FPU (floating point unit) designs already use the most efficient method of recoding the LZA output into a CLZ value and normalizer mux select signals. Therefore, the only method of speeding up the entire LZA function is apparently to begin computation of the LZA vector earlier than is currently performed.
The present invention addresses the foregoing need by providing a five-input LZA architecture which can compute the LZA based on five inputs rather than the two inputs used by all LZA implementations prior to this invention. By beginning computation of the LZA with five inputs, the LZA inputs can be moved up to two stages prior to the adder inputs. Usually, these two stages are composed of xe2x80x9cCarry-Save Addersxe2x80x9d (CSAs), also sometimes known as xe2x80x9cCompressors.xe2x80x9d By bypassing these two additional CSA stages, computation of the LZA function may begin and end sooner, allowing for significantly faster pipeline and thus processor speeds.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.